`default_nettype none

`define CLK_FREQ 27_000_000
`define DIV_CLK_DEFAULT (`CLK_FREQ / 1) // 默认时钟为1hz
`define GROUP_NUMS 8
`define GROUP_WIDTH 3
`define DEFAULT_VALUE ('b000_001_010_011_100_101_110_111)

module test_set_right_shift_reg_m (
    input rst_w_ni,
    input clk_w_i,
    input key_b_w_ni,

    output led_red_w_no,
    output led_green_w_no,
    output led_blue_w_no
);
    wire reg_clk_w;

    clk_even_div_m #(
        .DIV_DIV_2_CP_I(`DIV_CLK_DEFAULT / 2)
    ) default_div_i (
        .rst_w_ni(rst_w_ni),
        .clk_w_i  (clk_w_i),

        .clk_w_o(reg_clk_w)
    );

    wire [`GROUP_WIDTH-1:0] data_out_wp;
    right_shift_reg_m #(
        .WIDTH_CP_I(`GROUP_NUMS * `GROUP_WIDTH),
        .SHIFT_WIDTH_CP_I(`GROUP_WIDTH),
        .INIT_VALUE_CP_I(`DEFAULT_VALUE)
    ) shift_reg_i (
        .rst_w_ni(rst_w_ni),
        .clk_w_i(reg_clk_w),
        .shift_en_w_pi(1),
        .data_wp_i(data_out_wp),
        .set_en_w_pi(key_b_w_ni == 0),
        .set_wp_i(`DEFAULT_VALUE),

        .data_wp_o(data_out_wp),
        .get_wp_o()
    );

    assign led_red_w_no   = data_out_wp[0];
    assign led_green_w_no = data_out_wp[1];
    assign led_blue_w_no  = data_out_wp[2];
endmodule
